منابع مشابه
On Retiming Synchronous Data-Flow Graphs
Many common iterative or recursive DSP applications can be represented by synchronous data-flow graphs (SDFGs). A great deal of research has been done attempting to optimize such applications through retiming. However, despite its proven effectiveness in transforming single-rate data-flow graphs to equivalent DFGs with smaller clock periods, the use of retiming for attempting to reduce the exec...
متن کاملHalf-buffer retiming and token cages for synchronous elastic circuits
Synchronous elastic circuits borrow the tolerance of computation and communication latencies from the asynchronous design style. The datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses synchronous handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this paper. Half-buffer retiming allow...
متن کاملRetiming and Clock Scheduling for High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the performance of synchronous circuits. It is shown that when both long and short paths are considered, circuits optimized by the simultaneous application of retiming and clock scheduling can achieve shorter clock periods than optimized circuits generated by applying either of the two techniques separately. A novel mixed-...
متن کاملRetiming synchronous data-flow graphs to reduce execution time
Many common iterative or recursive DSP applications can be represented by synchronous data-flow graphs (SDFGs). A great deal of research has been done attempting to optimize such applications through retiming. However, despite its proven effectiveness in transforming single-rate data-flow graphs to equivalent DFGs with smaller clock periods, the use of retiming for attempting to reduce the exec...
متن کاملArchitectural Retiming: An Overview
Pipelining and retiming are two related techniques for improving the performance of synchronous circuits by reducing the clock period. Unfortunately these techniques are unable to improve many circuits encountered in practice because the clock cycle is limited by a critical cycle which neither technique can change. We present in this paper a new optimization technique that we call architectural...
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ژورنال
عنوان ژورنال: Algorithmica
سال: 1991
ISSN: 0178-4617,1432-0541
DOI: 10.1007/bf01759032